This application claims the priority benefit of Taiwan application serial no. 90128663, filed on Nov. 20, 2001.
1. Field of Invention
The present invention relates to a memory driver circuit. More particularly, the present invention relates to a driver circuit for controlling memory address addressing and commands.
2. Description of Related Art
Memory inside a personal computer (PC) system normally responds to a triggering signal from a memory control chip within the system. In other words, memory control is initiated by the falling edge of a chip select (CS) signal. According to the command signals and the memory address signals both submitted from the memory control chip, actions that need to be executed by the memory are determined. For example, the actions may include reading the memory content from a specified address or writing data into memory with a specified address. However, memory is also a place for holding and reading any data. Hence, the memory control chip of the PC needs to transmit a great volume of command signals and memory address signals. In general, to access memory data, the memory control chip will send the CS signal simultaneously to each memory unit within a memory module. In the meantime, the memory control chip will also transmit the memory signal first to a memory unit closest to the memory control chip, then transmit the memory signal to a memory unit farther away and so on sequentially. Consequently, when the falling edge of the CS signal arrives at a close memory unit to initiate the reading of a command signal, the memory unit is better able to obtain a command signal at a timing frame identical to the CS signal. On the contrary, when the falling edge of the CS signal arrives at a far away memory unit to read a command signal, due to instability or drift of the command signal, the memory unit can hardly obtain a command signal at a time frame identical to the CS signal. In extreme conditions, a memory unit situated at some distance from the control chip may execute the wrong action. Thus, the system designer must take into account the relationship between the transmission of command signals and memory addresses as well as the layout of memory trace lines on a main circuit board. In other words, both the maintenance period of command signals and the length of trace line leading from the control chip to the memory must be carefully considered.
Since the maintenance period for the CS signal is typically 1T period, the command signal is issued 2T cycles before the submission of the CS signal by convention. Because 2T cycles is a relatively long period, the memory unit can still read the command signal at a time frame identical to the CS signal when the memory unit is triggered by the CS signal, even if the signal transmission distance is long.
However, the two most common types of memory including the synchronous dynamic random access memory (SDRAM) and the double data rate synchronous dynamic random access memory (DDR SDRAM) already operate at a clocking rate of over 100 MHz. Under such high-speed operating condition, the number of cycles for transmitting a memory access command or the number of cycles taken for the command signal to transfer from the memory control chip to the memory unit for both SDRAM and DDR SDRAM is 2T cycles. Therefore, operating speed and performance of a computer system is cut back considerably. The effect is especially prominent when DDR SDRAM is used in the computer system.
Accordingly, one object of the present invention is to provide a memory address driver capable of providing a 1T or a 2T period timing command signal to the memory unit depending on actual operating conditions. Aside from increasing the capacity of a computer system to access memory data, the design also improves system stability.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a programmable memory controller. The memory controller includes a main memory controller, a command decoder, a period setting device, a command-sequencing device and a command signal output device. When the programmable memory controller needs to access data within a memory unit, the main memory controller issues a request signal. The command decoder receives the request signal, decodes the request signal and outputs a plurality of command signals. The command-sequencing device receives the command signals and orders the command signals according to a period setting signal submitted from the period setting device. The command signal output device receives the ordered command signals in sequence and controls the maintenance period of various ordered command signal cycles in the process of transferring to the memory according to the period setting signal provided by the period setting device.
The memory access structure inside the programmable memory controller according to this invention utilizes a plurality of command signals to control memory data access. The memory access structure includes a control chipset and a memory slot. The control chipset further includes a built-in programmable memory controller. When the control chipset needs to access data inside the memory, the built-in programmable memory controller inside the control chipset outputs the maintenance period for each command signal period. The memory slot receives the command signal for outputting to the memory.
In one preferred embodiment of this invention, the maintenance period for each command signal period may depend on the traveling distance of the command signal. The traveling distance of each command signal, in turn, depends on the length of trace line from the control chipset to a particular pin inside the memory slot.
Hence, according to the transmission distance of a command signal, a system having two different period maintenance periods, for example, a first period period (1T) and a second period (2T), may be established. In general, a preset distance of travel is often used as a criteria for assigning command signals to the first period or the second period. If travel distance of a command signal is smaller than the preset distance, the command signal is maintained for a first period. On the other hand, if travel distance of a command signal is greater than the preset distance, the command signal is maintained for a second period. In general, the preset distance is a measure of the length of a trace line from a memory slot pin to the control chipset.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.